1. Field of the Invention
This invention relates to an improved logic synthesis method for generating from register transfer levels (RTLS) a semiconductor integrated circuit. Particularly, this invention pertains to a logic synthesis method capable of generating a low-power semiconductor integrated circuit (SIC) and to a low-power SIC made by means of the logic synthesis method.
2. Description of Related Art
Various top-down design techniques have been employed for generating SICs. A top-down design technique represents a target SIC with RTL functional descriptions. More specifically, a target SIC is generated from RTL functional descriptions by means of logic synthesis.
FIG. 29 shows RTL functional descriptions. FIG. 30 shows a logic circuit, i.e., an SIC, generated from the RTL functional descriptions.
The functional descriptions specify respective register-to-register data transfers, at functional level. r1, r2, r3 and r4 are registers. func1, func2, func3 and func4 are functional descriptions of combinational circuits (CCs) each of which is connected between the registers. assign is a sentence descriptive of a connection relationship between a signal and a CC. Also, always is a sentence descriptive of a connection relationship between a register and a signal.
When synthesizing a logic circuit from the RTL functional descriptions shown in FIG. 29, the circuit is determined on the area/rate tradeoff curve by giving a constraint of the area and a constraint of the rate.
FIG. 30 shows the resulting logic circuit. 101, 103, 105 and 107 are flip-flop (FF) circuits mapped from r1, r2, r3 and r4 by means of logic synthesis. There is a direct correspondence between the FF circuits (101, 103, 105, 107) and the registers (r1, r2, r3, r4). 108 is a clock buffer. 100, 102, 104 and 106 are CCs and there exists a correspondence between these CCs and func1-func4. The CCs 100, 102, 104 and 106 are circuits that are mapped, as circuits on the area/rate tradeoff curve, from the FIG. 29 RTL functional descriptions.
The power consumption of an SIC, P, can be found by the following equation. EQU P=f.times.C.times.V.sup.2
where f is the operating frequency, C is the load capacitance and V is the supply voltage. There are three possible ways of reducing P. The first is to reduce f. The second is to reduce C. The last is to reduce V. Of these three ways the third one is considered the most attractive way since it is able to the most effectively reduce the power consumption.
However, there is the problem that as the supply voltage V decreases, a critical path of a great number of paths together forming a logic circuit, which has the maximum delay of all the paths, comes to have a greater delay.
With a view to providing a solution to the foregoing problem, Japanese Patent Application, published under Pub. No. 5-299624, proposes a technique. In accordance with this technique, low-speed logic gates, not required to operate at a high speed, are driven by a low-voltage source, whereas high-speed logic gates, required to operate at a high speed, are driven by a high-voltage source. This technique is trying to achieve a low-power SIC by driving logic gates forming a critical path by a high-voltage source and by driving other logic gates by a low-voltage source, with no increase in critical path's delay. This approach, however, produces the following drawbacks.
Suppose data is transferred from a slow logic gate driven by a low-voltage source to a fast logic gate driven by a high-voltage source. In this case, there is a need to arrange between these two logic gates a level shifter capable of converting a low-level output from the slow logic gate to a high level (see Japanese Patent Application, published under Pub. No. 5-67963). However each of the CCs shown in FIG. 30 is made up of great many logic gates (see FIGS. 31 and 32). In order to drive a critical path, represented by bold line, by high voltage, level shifters must be arranged at points marked with circles. In FIG. 31, a required number of level shifters is eight. In FIG. 32, twelve level shifters must be placed. A high-density SIC includes a great number of CCs, therefore containing a great number of logic gates. Accordingly, a critical path-containing CC of the high-density SIC requires a great number of level shifters. In addition, there are many CCs with a critical path. This means that the placement of an enormous number of level shifters is required. In high-density SIC design, it may be possible to determine where to place level shifters in a particular CC. However, it becomes considerably troublesome to determine where to place level shifters in an entire SIC. The placement of level shifters is therefore time consuming and design work becomes most complicated.